1. Field of the Invention
The invention relates to the field of MOS integrated circuits, particularly the forming of isolated silicon regions on a silicon substrate.
2. Prior Art
In the fabrication of metal-oxide-semiconductor (MOS) integrated circuits, steps are often taken to electrically isolate one device from another to eliminate or reduce parasitic paths between devices. If, for instance, field-effect transistors are fabricated on a silicon substrate without isolation, source or drain regions from two different transistors may act as an unwanted third transistor. Overlying interconnections such as aluminum lines disposed between the source of one transistor and the drain of another transistor, acts as a gate and can cause parasitic conduction.
Parasitic paths are even a greater problem in complementary MOS (CMOS) integrated circuits. There, the substrate, n+ or p+ regions of complementary transistors and the wells in which transistors of one conductivity type are formed can together form an unwanted transistor. Transistor action between these various regions can result in a parasitic path which destroys an integrated circuit. This problem is sometimes referred to as "latch-up".
Several processing techniques are currently used to reduce parasitic conduction. Field oxide regions are commonly used between adjacent transistors to isolate, for instance, the source of one transistor from the drain of another. These thicker oxides provide a less conductive path (a longer path) between adjacent transistors, and moreover, overlying lines are at a greater distance from the substrate decreasing their effectiveness as unwanted gates. A typical n+ to p+ field oxide is 6 microns in width for CMOS circuits, and thus, consumes a considerably amount of substrate area when compared to the area required to fabricate the field-effect transistor. In other cases, trenches are formed in the substrate and filled with an insulative material. This technique requires more complex processing, although it is effective, even with spacing as low as 1 micron.
Other techniques are also used in CMOS circuits to prevent latch up. For example, the circuits are formed in an epitaxial layer which layer is grown on a highly doped substrate. In other circuits, a thin layer is formed over an insulator such as in the silicon-on-sapphire (SOS) technology.
The present invention provides a departure from the prior art techniques described above. In the present invention, the crystalline structure of the substrate is used as a seed for the growth of an epitaxial-like layer formed over isolation regions.
Other processes for forming epitaxial-like layers from seeds are known. In general, these prior art processes use a single seed, do not fabricate devices on the seed window, or do not have electrical participation of the substrate in the final circuit. The closest prior art known to Applicant is: (1) Electronic Week, Aug. 6, 1984, page 31, "Britain Getting Its Act Together In SOI Technology In Bid To Get Jump On U.S. And Japanese Chip Makers"; (2) Electronic Week, Aug. 6, 1984, Pages 32-33, "Cambridge Lab Heats Wafers Top and Bottom"; (3) IEDM82, 16.4, Pages 433-436, Warabisako et al., "Characterization of Laser-SOI Double Si Active Layers By Fabricating Elementary Device Structures"; (4) IEDM82 16.1, Pages 420-423, T. I. Kamins "MOS Transistors in Beam-Recrystallized Polysilicon"; (5) J.Electrochem.Soc. September 1981, Pages 1981-1986 (Vol. 128, No. 9), Lam et al., "Single Crystal Silicon-On-Oxide By A Scanning CW Laser Induced Lateral Seeding Process"; (6) IEDM84 34.5, Pages 808-811, Herre et al., "Device Performances of A Submicron SOI Technology"; and (7) Journal of Crystal Growth 63 , 1983, pages 453-483, Fan et al., "Graphite-Strip-Heater-Zone-Melting Recrystallization of Si Films".